Shenzhen Advanced Institute processor chip performance big data research progress

On the evening of July 18, the review results of IEEE/ACM International Symposium on Microarchitecture (MICRO2018), a CCF Class A conference in the field of international architecture, were announced, and the paper Counter Miner: Mining Big Performance Data from Hardware Counters, a collaboration between Yirong Lu and Bin Sun, a master's student at the Center for Heterogeneous Intelligent Computing, Institute of Digital Research, Shenzhen Institute of Advanced Technology, Chinese Academy of Sciences, was accepted as a long paper (14 pages in double columns).

△ Left: outliers in the time series are replaced by normal values; Right: missing events in the time series are correctly filled

This work presents the concept of big data for processor chip performance and provides insight into the key techniques involved. First, the performance data generated by the processor chip in an efficient manner contains many errors, and the paper takes a comprehensive look at the distribution of this performance data and designs a linear regression-based error removal method based on the distribution. Experimental results show that the method reduces the error rate from 28% to 7%. On this basis, the paper quantifies the importance of performance events and the interaction between events, and summarizes six laws. Finally, the paper also designs a real-world scenario in which performance big data mining is used to efficiently optimize the performance of in-memory computing programs by a factor of four over traditional methods. The approach studied in the paper can also be used in many other ways, such as processor chip architecture performance optimization, energy consumption optimization, compiler optimization, task scheduling optimization, application performance optimization, etc.

△ Trend of model accuracy with the number of processor performance events

Founded in 1968, the MICRO conference is the top conference in the field of architecture, jointly sponsored by the Institute of Electrical and Electronics Engineers (Institute of Electrical and Electronics Engineers) and the American Computer Society (Association for Computing Machinery), dedicated to discussing and disseminating innovations in processor microarchitecture, and a variety of widely used techniques in modern processors come from MICRO conference articles. Attendees include researchers or students in the fields of microarchitecture, compilers, chips, and computer systems. The 2018 MICRO Conference will be held in Fukuoka, Japan, from October 20-24. Previously, no more than 10 papers from research institutes in mainland China have been accepted for this conference in the past 20 years.

Contribution: Center for Heterogeneous Intelligent Computing, Digital Institute

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